The present invention relates to a judging method and a preceding apparatus suitable for use in a transmitting apparatus such as a modem or the like, in particular, a transmitting apparatus which transmits data using a metallic line of a telephone line, a private line or the like.
A modem is generally used when data is transmitted over a telephone line or the like. There is thus a demand for a modem having a high transfer rate and low in price. Image information has particularly a great information quantity. A modem transmitting such image information needs a transfer rate of, for example, about 1.5 Mbps, higher than that of a modem used to transmit ordinary data.
FIG. 16 is a block diagram showing a structure of a general modem.
In FIG. 16, reference numeral 160 denotes a modem, reference numeral 161 denotes a receiving unit, and reference numeral 162 denotes a transmitting unit.
The receiving unit 161 has an analog/digital converting unit (an A/D converting unit) 161a, a line equalizer 161b, a demodulating unit 161c, a rolloff filter (ROF) 161d, an automatic gain control unit (AGC) 16le, an automatic equalizer (EQL) 161f, a carrier detecting unit (CD) 161g, a timing extracting unit 161h, a clock signal generating unit 161i, etc.
The transmitting unit 162 has a logic processing unit 162a, a rolloff filter (ROF) 162b, a modulating unit 162c, and a digital/analog converting unit (D/A converting unit) 162d.
In the modem having the above structure, a signal point of a transmit data signal is generated through a process conducted by the logic processing unit 162a, and the generated signal point is undergone a waveform shaping process by the rolloff filter 162b, modulated by the modulating unit 162c, after that, converted into an analog signal by the D/A converting unit 162d and transmitted as a data signal.
A received analog data supplied to the receiving unit is converted into a digital signal by the A/D converting unit 161a. After that, the received signal is demodulated by the demodulating unit 161c, undergone a waveform shaping process by the ROF 161d, then supplied to the AGC 161e. The AGC 161e conducts a gain control on the received signal, then supplies the signal to the EQL 161f.
In order to prevent propagation of an error of transmit data, a precoder is provided in the transmitting unit (a part functioning as the above logic processing unit 162a, for example) of the modem.
FIG. 17 is a diagram showing a data transmitting system using partial response (called PR, hereinafter). Partial response is one of non-Nyquist transmission systems.
In FIG. 17, reference numeral 171 denotes a PR filter of a transmitting-side apparatus, reference numeral 172 denotes a low-pass filter (LPF) of a receiving-side apparatus, and reference numeral 173 denotes a judging circuit.
The PR filter 171 adds input data A.sub.K to preceding data A.sub.K-1, and outputs a result as data Y.sub.K to a line, whose equivalent circuit is as shown in FIG. 18. As shown in FIG. 18, data inputted to the PR filter 171 is stored in a PR tap 171a. An adder 171b adds a value stored in the PR tap 171a to data inputted next to the PR filter 171 and outputs a result.
The data Y.sub.K is transferred to the receiving-side apparatus over a line, and received as data R.sub.K by the receiving-side apparatus. The received data R.sub.K is inputted as data L.sub.K through the LPF 172 to the judging circuit 173, in which a signal-point judgement and the like are conducted.
Here, the data L.sub.K is expressed as: EQU L.sub.K =R.sub.K =Y.sub.K =A.sub.K +A.sub.K-1
The judging circuit 173 judges the inputted data L.sub.K, and outputs data D.sub.K representing a result of the judgement. Here, the result D.sub.K of the judgement is expressed as: EQU D.sub.K =A.sub.K =R.sub.K -A.sub.K-1
Therefore, if A.sub.K-1 is determined, the next transmit signal A.sub.K can be determined on the basis of the received signal R.sub.K.
However, PR has a disadvantage that if the result A.sub.K-1, of reception is erroneously judged, judgements on the following signals A.sub.K, A.sub.K+1, . . . result in failure, which leads to propagation of the error. To prevent this, it is possible to provide a precoder in the front stage of the PR filter 171.
FIG. 19 is a diagram showing a system in which the precoder and the PR filter 171 are connected. In FIG. 19, like reference characters designate like or corresponding parts in FIG. 17. Reference numeral 193 denotes a modulo (mod) precoder, and reference numeral 194 denotes a modulo judging unit.
FIG. 20 shows equivalent circuits of the modulo precoder 193 and the PR filter 171 shown in FIG. 19. Here, the PR filter 171 is the same as that shown in FIG. 18. The modulo precoder 193 is configured with a modulo judging circuit 193a, a precoder tap 193b and an adder 193c. The precoder tap 193b stores an output of the modulo judging circuit 193a, the adder 193c then calculates a difference between a precoder tap value and input data.
The modulo precoder 193 calculates a difference between the input data A.sub.K and the preceding output B.sub.K-1 from the modulo precoder 193, and conducts a modulo operation on the difference. This is described in "Principle of Data Communication" p.p. 97-106, Lattice., for example.
Here, the output L.sub.K of the LPF 172 of the receiving-side apparatus is: EQU L.sub.K =R.sub.K =Y.sub.K =B.sub.K +B.sub.K-1 =mod(A.sub.K -B.sub.K-1)+B.sub.K-1
Therefore, a judgement output D.sub.K of the judging circuit 174 is: ##EQU1##
By providing the modulo precoder 193 in the transmitting-side apparatus, it becomes unnecessary to make a judgement on the data A.sub.K on the basis of the data A.sub.K-1, received in the preceding occasion in the receiving-side apparatus so that an error is not propagated.
However, the modulo operation causes the following problem. Here, the problem will be described by way of an example where the number of signal points are 64 values.
The adder 193c calculates a difference between data inputted to the modulo precoder 193 and a value stored in the precoder tap 193b, and outputs a result to the modulo judging circuit 193a. If constellated on a vector plane, the signal points of 64 values can be constellated in 8.times.8. For this, a "limit frame" is set to +/-16.
FIG. 21(a) shows signal point constellation of 64 values, whereas FIG. 21(b) shows a setting of a limit frame. It is assumed here that in each of four small rectangular sections (refer to 1 through 4), signal points of 16 values are constellated.
Numbers [refer to (1) through (4)] in outer sections shown in FIG. 21(b) correspond to encircled numbers (refer to 1 through 4) in four inner sections [or four regions in FIG. 21(a)], which shows that these outer regions are shifted from corresponding regions in FIG. 21(a) as a result of the modulo operation.
In FIG. 21(a), the signal points are constellated in a region of +/-8. Namely, a maximum value of the signal is +/-8. The modulo precoder 193 calculates a difference between input data and a precoder tap value, it is then judged whether a value of the difference exceeds +/-16 (/times a region in which the signal point is located). If the value of the difference exceeds +/-16, the modulo operation is conducted on the result.
An output of the modulo precoder 193 is inputted to the PR filter 171. The PR filter 171 adds the output of the modulo precoder 193 to a value outputted in the preceding occasion from the modulo precoder 193 and stored in the filter tap 171a.
Assuming here that a precoder tap value is, for example, -16. If an input to the modulo precoder 193 is -7, an output of the modulo precoder 193 is: EQU -7-(-16)=+9
Since the precoder tap value is equal to a value stored in the PR filter tap 171a, an output of the PR filter 171 is: EQU +9+(-16)=-7
so that a value equal to a value inputted to the modulo precoder 193 is obtained.
To the contrary, if an input of the precoder 193 is +1, a difference between the precoder tap value and the input value is: EQU +1-(-16)=+17
so that the above result exceeds a range of the limit frame. For this, the modulo operation is conducted in this case. As a result, a value +1 obtained by subtracting 16 from +17 is outputted from the precoder.
When the precoder output is added to the PR filter tap value -16, a result is: EQU +1-(-16)=-15
This value is different from the precoder input (+1).
If the precoder tap value exceeds the limit frame of the precoder, the modulo operation is conducted to decrease a new precoder tap value, as above. If no module operation is conducted, the precoder tap value is gradually increased, and the precoder tap value may be dispersed. For this, the modulo operation is necessary.
However, an output of the PR filter 171 is shifted by a quantity shifted in the modulo operation, which causes generation of an abnormal peak signal point.
The present applicant has proposed a technique as to a precoder in which a problem caused by the modulo operation has been overcome (Japanese Laid-Open Publication No. 7-273827).
In the above technique, there is employed a circular limit frame as shown in FIG. 22.
A distance from the origin on a vector plane corresponds to a magnitude of a power of a signal. If the limit frame is rectangular as shown in FIGS. 21(a) and 21(b), a power of a signal point at each of the four corners becomes large as compared with those of the others. Since a power of a signal point exerts an affect on the S/N ratio, it is desirable that a power of a signal point is uniform as much as possible. The limit frame shown in FIG. 22 is circular so that a maximum peak value of the signal point power becomes uniform.
Further, according to the above technique, a plurality of signal points are set to an original signal point. If there is possibility that an output of the precoder exceeds the limit frame, the precoder tap coder process is conducted on added signal points along with the original signal point, and a signal point having a minimum signal point power (i.e., a signal point closest to the origin on the vector plane) is selected among these signal points and outputted.
For instance, two signal points B and C are additionally generated in respect to an original signal point A in FIG. 22. In FIG. 22, reference numeral 221 denotes a region in which the original signal point is located, and reference numeral 222 denotes the circular limit frame. The signal points additionally generated are set outside the region in which the original signal point is located.
The signal points A through C are located at 120.degree. apart. However, since the signal points have been quantized, it is sometimes difficult to locate three signal points at exact 120.degree. intervals. In such case, the three signal points are located at angles as closer to 120.degree. as possible.
FIG. 23 shows an example where the precoder tap value is positioned on the circular limit frame. In FIG. 23, reference numeral 231 denotes the limit frame. S1 through S8 denote signal points (precoder tap values) in eight kinds constellated on the limit frame.
On each of the signal points, the three signal points shown in FIG. 22 are overlaid. The origin of the three signal points (refer to FIG. 22) is overlaid on the signal point located on the limit frame. The signal points A through C in FIG. 23 are candidates for a signal point outputted from the precoder this time.
By selecting one signal point located inside the limit frame among the three candidates, it is possible to avoid the above problem generating upon the modulo operation conducted when the precoder tap value exceeds the limit frame. By selecting a signal point closest to the origin among signal points located inside the limit frame, it is possible to select a signal point having a minimum power of a signal point to be transmitted, thereby improving the S/N ratio of a transmit signal.
The number of signal points additionally generated in respect to an original signal point may be not always two. One signal point (two signal points in all when the original signal point is added) or three signal points (four signal points in all when the original signal point is added), for example, may be employed.
If the number of signal points is two, both of the signal points may be outside the limit frame depending on a position of the precoder tap value on the limit frame since an angle made by the two signal points is 180.degree.. If each of intervals of a plurality of signal points is 120.degree. or less, at least one signal point falls within the limit frame no matter which position on the limit frame the precoder tap value is located in. In consequence, it is desirable that a total number of the signal points are three or more.
Here, it is possible to store information as to each signal point (coordinates on the vector plane) in a ROM. If a total number of the signal points increases, the number of signal points to be stored in the ROM increases. For this, it is desirable that a total number of signal points, which are an original point and added signal points, is as small as possible.
It is most desirable that a total number of an original signal point and added signal points are three.
FIG. 24 is a diagram showing an example of an equivalent circuit of a precoder apparatus 240 which selects a signal point located inside the limit frame among such three candidates A through C for a signal point and conducts the precoder process using the selected signal point.
In FIG. 24, thick solid line shows a vector signal, whereas thin solid line shows a scalar signal. Outputs from squaring circuits 242 through 248 are scalar signals, and another outputs are basically vector signals.
A plurality of signal points generating circuit 241 generates the signal points B and C shown in FIG. 22 according to input data representing the signal point A. The plurality of signal points generating circuit 241 is configured with a ROM, which outputs the signal points B and C determined primarily with information of the signal point A as an address.
The information of the signal point A is inputted to the squaring circuits 242 and 243, and squared to determine a power (a position from the origin of the vector plane) of the signal point. Following that, outputs of the square circuits 242 and 243 are compared with reference values TH1 and TH2 by adders 252 and 253, respectively, and results of the comparison are supplied to an original signal point region judging circuit 256.
The original signal point region judging circuit 256 judges which region shown in FIG. 25(A) on the vector plane the original signal point A is located in, according to values fed from the adders 252 and 253.
FIG. 25(A) is a diagram showing a vector plane. As shown in FIG. 25(A), the vector plane is divided into three regions 1, 2 and 3.
Here, it is selected according to a region in which the original signal point is included whether the original signal point A is outputted as it is or one signal point is selected among the signal points A, B and C. If the original signal point is in an inner region 1, it is assumed that a precoder output does not exceed the limit frame so that the original signal may be outputted as it is. If the original signal point is included in an outer region 3, it is assumed that the precoder output exceeds the limit frame so that a signal point having the smallest power is selected among the three signal points.
If the original signal point is included in a region 2, a process to select a signal point is changed according to the precoder tap value since whether the precoder output exceeds the limit frame or not is determined according to the precoder tap value.
The reference value TH1 in FIG. 25(A) is a value corresponding to a boundary between the region 1 and the region 2, whereas the reference value TH2 is a value corresponding to a boundary between the region 2 and the region 3. The original signal point region judging unit 256 judges which region shown in FIG. 25(A) the original signal point is included in, according to magnitudes of outputs of the adders 252 and 253.
Reference numeral 260 denotes a precoder tap, in which a value outputted from an adder 261 is stored. An output of the precoder tap 260 is supplied to the adder 261 along with the squaring circuit 244 and 245, and adders 249, 250 and 251.
Each of the squaring circuits 244 and 245 squares the precoder tap value to determine a power of the precoder tape value (a distance from the origin). Outputs of the square circuits 244 and 245 are supplied to the adders 254 and 255, and compared with reference values TH3 and TH4, respectively.
The reference values TH3 and TH4 are values used to divide the regions a, b and c on the precoder tap plane in FIG. 25(B). The precoder tap value region judging circuit 257 judges which region among regions a, b and c shown in FIG. 25(B) the region of the precoder tap value corresponds to on the basis of a result of comparison made between outputs of the adders 254 and 255. An ABC optimum value selecting circuit 258, which will be described later, switches whether the original signal point is outputted or one signal point is selected among three signal points [refer to a table in FIG. 25(C)].
The signal points A, B and C are inputted to the adders 249, 250 and 251 along with the precoder tap value. Each of the adders 249, 250 and 251 calculates a difference between the precoder tap value and the corresponding signal point A, B or C. Following that, outputs of the adders 249, 250 and 251 are supplied to the squaring circuits 246, 247 and 248, respectively. Each of the squaring circuits 246, 247 and 248 calculates a power as a result of the difference between the precoder tap value and the signal point. A minimum power signal point selecting circuit 259 selects a signal points whose power obtained as a result of the difference between the precoder tap value and the signal point is closest to the origin of the vector plane, and outputs a result.
An ABC optimum value selecting circuit 258 receives the signal points A, B and C, and outputs of the original signal point region judging circuit 256, a precoder tap value region judging circuit 257 and the minimum power signal point selecting circuit 259, and outputs either what is selected as an optimum signal point among the three signal points A, B and C or the original signal point to the adder 261.
The above precoder process has been conducted by a DSP. In the case of a modem whose transfer rate is 28.8 kbps and bau rate is 3.3 kbau, a process cycle number of the modem was 1000 cycles per bau rate.
There is, however, a demand for a modem transferring image information in these years. To meet the demand, a modem whose transfer rate is 1.5 Mbps and bau rate is 192 kbau has been proposed, for example. If a DSP suitable for use in a modem whose transfer rate is 28.8 kbps is employed to the above modem, the number of cycles usable for the precoder process per bau rate is only about 50 cycles.
In the modem communicable at a transfer rate 1.5 Mbps and a bau rate 192 kbau, the number of cycles in total per bau rate in the DSP is about 180 cycles at most. This means that the precoder process occupies 50/180 of the whole process, which is a very large proportion, in order to conduct the above preceding process. As a result, the modem not only has to bear a large load of the process, but also has little margin for the precoder process.
Since the modem whose transfer rate is 1.5 Mbps has to process high-speed signals, the modem requires a certain process cycle number for another processes. It is therefore necessary to provide a number of DSPs in the modem in order to conduct a lot of processes within a short period. As this, it is difficult to realize a modem which can conduct the process at a high speed.